Optimizing BNC PCB Footprint Designs for Digital Video Equipment

How to choose a BNC connector and properly design the BNC footprint on a high-speed printed circuit board — with the goal of meeting the tight requirements for SMPTE return loss. This article provides an overview of the types of BNCs in the broadcast video market, the test to determine the BNC’s electrical quality, common mistakes in BNC footprint designs, techniques for designing good BNC footprints and the use of 3D simulation tools to determine layout decisions.

By Tsun-kit Chin
Applications Engineer, Member of Technical Staff National Semiconductor Corp.

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Video/Imaging DesignWire
(9/10/2010 1:05:28 AM)

Testing the BNCs with National’s LMH0387
Now, the BNC footprints are optimized with the 3-D EM simulator. Several BNC types and their optimized footprints are implemented onto the LMH0387 evaluation boards for validating their system performance.

The LMH0387 is the industry’s first single-chip adaptive cable equalizer and cable driver that enables one BNC to be shared as an input port or an output port. It has a built-in termination and return loss network to compensate the capacitance from the integrated circuit and simplifies high speed board layout for meeting SMPTE return loss with good margin.

Figure 19: Simplified schematic for the LMH0387 Configurable IO

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Figure 19 illustrates the simplified circuit of the evaluation board. The LMH0387 is connected to the BNC through an AC coupling capacitor (4.7µF). To achieve good return loss, the LMH0387 is placed close to the BNC port, and connected to the BNC with a 75Ω trace. Ground relief technique is also used for the large landing pads of the 4.7µF AC coupling capacitor to minimize impedance discontinuity.

TDR impedance measurements and return loss measurements are performed at the BNC port.

Figure 20: Photographs of the LMH0387 with straight and right-angle through-hole BNCs

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Figure 20 shows the photographs of two evaluation boards mounted with straight and right angle through-hole BNCs. Their impedance profiles measured with a TDR are shown in Figure 21.
Figure 21: Impedance profiles of BNCs, footprints and traces to the LMH0387

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Figure 22 shows their return loss plots demonstrating 5-10 dB margin from the SMPTE limits.

Figure 19: Plots of return loss at BNC ports meeting SMPTE requirements with margins

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Figures 23-25 are another set of measurement plots for edge-mount and surface-mount BNCs.

Figure 23: Photographs of the LMH0387 with edge-mount and right-angle surface-mount BNCs

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Figure 24: Impedance profiles of BNCs, footprints and traces to the LMH0387

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Figure 25: Plots of return loss at BNC ports meeting SMPTE requirements with margins

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In this article, several common problems in BNC footprints are discussed, and several design techniques for transparent footprint designs are presented. The best design is the use of connectors with the smallest signal pin, so there is no need to design any special board structures. For connectors with larger signal pins, whether it is an edge-mount or a through-hole type, it is possible to design a controlled impedance footprint with good performance. Always use the smallest pad or smallest hole possible. Walk along the signal path, examine the board structure one by one, look for the parasitic inductance and capacitance along the path, and find ways to shave off the excess and bring the impedance to the target value.

While the principles used in this article apply to footprint designs, they are also valid for other component landing pads as well. High-speed board designs have gone beyond connectivity from point A to point B. There are many subtle layout decisions that have consequences in the electrical performance. Three dimensional electromagnetic simulation tools aid engineers in making the important layout decisions and achieving the target electrical behavior. The time domain reflectometer is a useful instrument for board debugging and identifying where the impedance changes occur. Good signal launch is a starting point to achieve good signal quality and meet return loss requirements along with other circuitry on the board.

The author would like to acknowledge the collaboration work with Travis Ellis of Samtec for running 3-D simulations to optimize the footprints for the Samtec True75™ BNCs used in the LMH0387 evaluation boards.

1. The Society of Motion Pictures and Television Engineers publishes many SMPTE standards on the serial digital video interface. Some of these standards are:
– SMPTE 259M-2006: SDTV Digital Signal/Data – Serial Digital Interface
– SMPTE 292M-1998: Bit Serial Digital Interface for High Definition Television Systems
– SMPTE 424M-2006: 3Gb/s Signal/Data Serial Interface
2. United States Patent 6765298: “Substrate pads with reduced impedance mismatch and methods to fabricate substrate pads”
3. Some 3-D electromagnetic simulators: Ansoft HFSS, Agilent EMDS/ADS
4. Datasheets of LMH0384, LMH0303, LMH0387 and many other SDI devices can be found at www.national.com/sdi/
5. True75™ is a trade-mark of Samtec. Information on Samtec True75™ BNCs can be found in Samtec website: www.samtec.com/rfcable/Standard_RF_PCB_Components.aspx.

About the author
Tsun-kit Chin is a member of the technical staff for National Semiconductor’s High Speed Product Division. He also is a member of the application team supporting serial digital video and signal conditioning LVDS products in National’s High Speed Data Products Group. Previously, Tsun-kit worked as an application engineer supporting various National analog ICs ranging from voice band telecom products to data communications ICs for FDDI and Ethernet. He received his bachelor’s degree in electronic engineering from the Hong Kong Polytechnic University. Tsun-kit enjoys problem solving and laboratory explorations. He can be reached at tsun-kit.chin@nsc.com.

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