Optimizing BNC PCB Footprint Designs for Digital Video Equipment

How to choose a BNC connector and properly design the BNC footprint on a high-speed printed circuit board — with the goal of meeting the tight requirements for SMPTE return loss. This article provides an overview of the types of BNCs in the broadcast video market, the test to determine the BNC’s electrical quality, common mistakes in BNC footprint designs, techniques for designing good BNC footprints and the use of 3D simulation tools to determine layout decisions.

By Tsun-kit Chin
Applications Engineer, Member of Technical Staff National Semiconductor Corp.

Page 7 of 8
Video/Imaging DesignWire
(9/10/2010 1:05:28 AM)

BNC Footprint Optimization
BNC footprint designs involve placement of anti-pads, or relief in the GND and VCC inner layers, or placement of surface GND strips to introduce just enough parasitic capacitance for maintaining the desirable characteristic impedance. The footprint is dependent on the signal pin diameter of the BNC, as well as the number of power plane layers in the board. In some cases, the footprint is designed to deviate from the nominal 75Ω in order to compensate for a small imperfection in the BNC itself. Hardware engineers have to optimize BNC footprints based on past experience and in many cases, multiple board re-spins are common.

BNC footprint design is best optimized with the use of 3-dimensional electromagnetic simulations. Starting with the BNC’s 3-dimensional model (mechanical dimensions and material properties), the proposed footprint structure, and the board’s properties (trace width, stack-up and material properties) are entered into the 3-D EM simulator3. Frequency domain simulations are performed to ensure compliance to design goals on return loss and insertion loss. Simulated TDR can also be done to examine the impedance profile of the BNC and the footprint.

BNC vendors, with the complete knowledge of the BNC’s model, are best in running such simulations with the customers’ input on board stack-up. The simulation example shown in this section is courtesy of Samtec, a connector supplier.

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Figure 16: 3-D model of Samtec’s right-angle BNC and its footprint on a PCB

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Figure 17: Simulated return loss of BNC and its footprint

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Figure 18: Simulated insertion loss of BNC and its footprint

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NEXT: Testing the BNCs with National’s LMH0387

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