Intelligent Video Surveillance System Example
ADI and the Department of Automation at Tsinghua University in Beijing have collaborated on a video surveillance system based on a Blackfin ADSP-BF561 dual-core processor. ADI supplied the optimized H.264 encoding algorithm featuring high quality and high performance, while Tsinghua University developed the auto tracking algorithm on BF561. The system block diagram is shown in Fig. 1.
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Figure 1: Diagram of a smart surveillance module, based on the ADSP-BF561.
The H.264 encoding algorithm module is a downloadable Blackfin software module provided by ADI. It completely supports dynamic configuration allowing users to vary the code rate, frame rate, critical frame intervals and the quantification values, etc., during the system runtime, according to the variation of the scenario and network bandwidth. Multiple systems, from 80kb/sec CDMA network to 3Mb/sec DVRs, may use the same set of function libraries to achieve ideal encoding quality, demonstrating high adaptability and flexibility.
The smart tracking algorithm from Tsinghua University utilizes the background subtraction method of single Gauss background modeling to detect motion. In the object classification phase, the classification based on motion properties and the classification based on shape information are combined, so that the categorization of moving objects can be realized by distilling the aspect ratio, gradient bar chart and moving periodicity of human bodies and vehicles.
When tracking objects of the same class, the direction and distance of the mass center displacement of moving objects is determined between successive frames, by making use of the region-based algorithm. Based on algorithms utilizing the three phases outlined above, the system can implement functions like crowd tracking, intrusion detection, people/vehicle counting, left object detection, camera tamper detection and displacement alarm.
In the dual-core ADSP-BF561 system, Core A is used for the implementation of H.264 compression, and Core B is used to deliver the video analysis. Both the uC-OSII operating system and RTP/TCP-IP protocol stacks run on Core A. YUV 4:2:2 video frames are transferred to the buffers in SDRAM, through a Parallel Peripheral Interface (PPI) via DMA. Core A and B share the frame buffer. Core B initiates the memory DMA, transferring the Y (brightness) component of a video frame to the line buffer in the on-chip memory L1 SRAM of Core B. Core B then calculates the background modeling, subsequent motion detection, and object tracking on the Y component in the line buffers.
If an object of the pre-specified classifications appears in the visible region, Core B will send an interrupt signal to Core A, and Core A will send an alarm message to a local console through a UART port, or send an alarm message to the remote console through a network interface. Core B may further modify the frame buffer, to add a rectangular highlight frame on the object for identification. Core A may also receive the video brightness and chroma data from the frame buffer.
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