HD Video Transcoding Strategies using Multicore Media Processors: Part 2 – Flexible Architecture

Delivering video across a variety of platforms involving multiple codecs can be efficiently handled by multicore media processors. Part Two explains the architectural requirements for flexible processing.

By Bahman Barazesh, Senior Technical Manager, and George Kustka, Senior Video Architect, LSI Corporation

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Video/Imaging DesignWire
(4/12/2010 8:30:02 AM)

In part one, we described the most common video standards and noted how the existence of so many widely used standards is a testament to the dynamic nature of video coding technology. To conclude our two-part series, we’ll address the flexible, multicore, media processor-based approach taken by silicon manufacturers.

Programmable Multicore Media Processors

As multiple video and audio formats emerge, devices that support them become increasingly complex. This situation leads to more costly and complex semicon­ductor designs. As video is such a demand­ing application, many capabilities must be considered when deploying a video-specific product. A programmable multicore solution provides the necessary flexibility and power efficiency.

A significant percentage of real-time cycles in video coding are spent managing control and data manipulation. For example, the computation required for functions, such as transforms, quantization, motion compensation, and filtering, is very large. At first thought, this scenario suggests that dedicated hardware can be added to facilitate real-time intensive functions. On the other hand, modern video standards do not process all blocks of video the same way. A large number of variations exist for any given block that is coded. Video codecs use this large menu of techniques to find efficient solutions for each block. The number of reference pictures used for prediction of any given block has also increased. Added levels of complexity are required for Scalable Video Coding (SVC), which defines even more encoding options and enhancement levels. A platform for a modern video codec must be able to process control-sensitive data and real-time computation efficiently to meet system power and throughput requirements.

Data access has become more critical with the evolution of more complex video- compression algorithms. For a codec to be efficient, data flow and processing should be pipelined to limit random access to external storage. Using fast cache memory for random access and large external DDR memory for picture storage allow efficient planning of memory access. In addition, leveraging hardware support in the processor increases codec performance. Enhanced control and change of flow instructions are better suited to ensure codec efficiency than dedicated hardware solutions, because they can provide the processing throughput, memory access, and flexibility needed.

Each element of event processing or management might require slightly different forms of computation. These elements dictate the overall architecture of the system. Using a single processor core can result in an inefficient architecture because the need for increased clock speed or more cores requires a more costly and power-hungry device. By dedicating a programmable core to different functions, computational tasks and efficiency can be optimized. Alternative partitioning of codec functions can achieve the same goals of density and efficiency in other ways. It is desirable that the software architecture be flexible enough to handle multiple system applications with minimal change, which simplifies system use and reduces costs of software support.

The important message here is that media processors with high-performance cores can provide high levels of throughput and performance while keeping the flexibility to adapt to future requirements and applications. This flexibility is invaluable in maintaining the software and controlling the lifetime cost of the system.

Table 1: Key Features of Multimedia-Targeted Multicore DSPs

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