DisplayPort Interface
The input stage consists of a DisplayPort SerDes, which receives data at 2.7 Gbps per lane, with up to four lanes. To identify when a monitor is plugged into a PC, there is a Hot Plug Detect (HPD) signal that is used to establish the link. The HPD signals the source to read the status and configuration registers in the receiver and to establish a link through a process called link training. During the status and configuration integration process, the source and receiver will also establish whether all of the four lanes are required.
Unique to DisplayPort is the Auxiliary (AUX) channel, which is a slow speed “side channel” communication channel for link management, status, configuration and control by the source. The AUX channel uses Manchester II encoding for transmitting half-duplex, bi-directional data. The source is the master, and the receiver is the slave - so all transactions are initiated by the source. The AUX channel provides 1 Mbps of data with a max 16-byte transaction taking no more than 500 microseconds (see Figure 3).
Figure 3. DisplayPort Using the Auxiliary Channel and Hot Plug Detect
After a receiver is connected to a source, the source will need to read the Extended Display Identification Data (EDID) to determine information about the monitor, manufacturer, model, timing, size, resolution and initial luminance of the panel. This standardized EDID data structure is stored in an external EEPROM. The source reads the EDID data from the EEPROM by issuing an AUX channel command to do an I2C read. This information is used to determine the required number of DisplayPort lanes that will be required.
SerDes Initialization
The first part of SerDes link training starts with the source transmitting a 101010 pattern at 2.7 Gbps for the SerDes clock and data recovery logic to lock to the exact frequency. After the receiver confirms frequency lock, the source will transmit a series of symbols that include more complex patterns to ensure the logical connection is made during the second part of link training. This link training part also allows the receiver to request pre-emphasis from the source and to enable signal equalization within the receiver. The source and receiver try a variety of signaling levels to minimize the noise and lower the BER. The differential “eye” pattern is open at the receiver on a 3-meter cable and will likely be closed when using 15-meter or longer cables. If the error rate is too high at 2.7 Gbps, the receiver will signal to the source to reduce the frequency to 1.62 Gbps and re-optimize the settings. After the receiver confirms the logical link has been established, the link is ready to transfer data. The HPD signal allows for the receiver to signal to the source that attention is required.
The output of the SerDes logic level is 8-bit packetized data from the link. The receiver will route the main link data to the video processor, and then look for secondary packet data, which may be audio or another video channel. The receiver will then route the audio data to the audio module and the secondary video to a transmitter to be sent to another panel receiver.
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